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Serial Peripheral Interface - Master/Slave with FIFO
The DSPI_FIFO is a fully configurable SPI master/slave device, which allows you to configure polarity and phase of a serial clock signal SCK. It allows a microcontroller to communicate with serial peripheral devices, but also to communicate with an interprocessor in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on two independent serial data lines.
The DSPI_FIFO data is simultaneously transmitted and received. What's more important, this is a technology independent design, that can be easily implemented in a variety of process technologies. The DSPI_FIFO system is flexible enough, to interface directly with numerous standard product peripherals, from several manufacturers. The system can be configured as a master or as a slave device, with data rates as high as CLK/4. The clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols, to accommodate most available, synchronous serial peripheral devices. When the SPI is configured as a master, the software selects one of eight different bit rates for the serial clock.
The DSPI_FIFO automatically drives selected by the SSCR (Slave Select Control Register) slave outputs (SS7O - SS0O) and addresses the SPI slave device to exchange serially shifted data. Error-detection logic is included to support interprocessor communications. A write collision detector indicates, when an attempt is made to write data to the serial shift register, while a transfer is in progress. A multiple-master mode-fault detector automatically disables DSPI output drivers, if more than one SPI device simultaneously attempts to become a bus master.
The DSPI_FIFO supports two DMA modes: single transfer and multi-transfer. These modes allow the DSPI_FIFO to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers.
Our solution is fully customizable, which means it is delivered in the exact configuration to meet users? requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow
The DSPI_FIFO data is simultaneously transmitted and received. What's more important, this is a technology independent design, that can be easily implemented in a variety of process technologies. The DSPI_FIFO system is flexible enough, to interface directly with numerous standard product peripherals, from several manufacturers. The system can be configured as a master or as a slave device, with data rates as high as CLK/4. The clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols, to accommodate most available, synchronous serial peripheral devices. When the SPI is configured as a master, the software selects one of eight different bit rates for the serial clock.
The DSPI_FIFO automatically drives selected by the SSCR (Slave Select Control Register) slave outputs (SS7O - SS0O) and addresses the SPI slave device to exchange serially shifted data. Error-detection logic is included to support interprocessor communications. A write collision detector indicates, when an attempt is made to write data to the serial shift register, while a transfer is in progress. A multiple-master mode-fault detector automatically disables DSPI output drivers, if more than one SPI device simultaneously attempts to become a bus master.
The DSPI_FIFO supports two DMA modes: single transfer and multi-transfer. These modes allow the DSPI_FIFO to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers.
Our solution is fully customizable, which means it is delivered in the exact configuration to meet users? requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow
Features
- SPI Master
- Master and Multi-master operations
- Two modes of operation: SPI mode and FIFO mode
- 8 SPI slave select lines
- System error detection
- Mode fault error
- Write collision error
- Interrupt generation
- Supports speeds up 1/4 of system clock
- Bit rates generated 1/4 - 1/512 of system clock.
- Four transfer formats supported
- Simple interface allows easy connection to microcontrollers
- SPI Slave
- Slave operation
- Two modes of operation: SPI mode and FIFO mode
- System error detection
- Interrupt generation
- Supports speeds up 1/4 of system clock
- Simple interface allows easy connection to microcontrollers
- Four transfer formats supported
- Fully synthesizable
- Two DMA Modes allows single and multi-transfer
- In the FIFO mode transmitter and receiver are each buffered with 16/64 byte FIFO's to reduce the number of interrupts pre-sented to the CPU
- Optional FIFO size extension to 128, 256 or 512 Bytes
- Available system interface wrappers:
- AMBA - APB Bus
- Altera Avalon Bus
- Xilinx OPB Bus
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
Deliverables
- Source code:
- VHDL Source Code or/and
- VERILOG Source Code or/and
- Encrypted, or plain text EDIF netlist
- VHDL & VERILOG test bench environment
- Active-HDL automatic simulation macros
- ModelSim automatic simulation macros
- Tests with reference responses
- Technical documentation
- Installation notes
- HDL core specification
- Datasheet
- Synthesis scripts
- Example application
- Technical support
- IP Core implementation support
- 3 months maintenance
- Delivery the IP Core updates, minor and major versions changes
- Delivery the documentation updates
- Phone & email support
Applications
- Embedded microprocessor boards
- Consumer and professional audio/video
- Home and automotive radio
- Low-power applications
- Communication systems
- Digital multimeters
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