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Serial Peripheral Interface (SPI)
The SPI provides full-duplex, synchronous, serial communication between peripheral devices and is programmable from a host CPU through the AMBA APB bus. It transfers and receives data simultaneously using a common data clock, which synchronises the transfer of serial data. Transfer size and format are configurable within the SPI. The SPI can be configured to operate as a master or slave module. When operating in master mode, the SPI controls data transfers to and from slave modules. In master mode, it does not respond to any transfers initiated by another master SPI and only receives data while simultaneously transferring data. When operating in slave mode, the SPI responds to requests and slave select signals from a master SPI and does not initiate any transfers. A slave SPI only transmits data while simultaneously receiving data.
Features
- Full-duplex operation, simultaneous receive and transmit
- Separate transmit and receive FIFOs
- Operates in master or slave mode
- ARM® AMBA® APB slave interface to SoC
- Supports up to four external peripherals in master mode
- Optional reference clock input block
- Programmable master mode clock frequencies
Deliverables
- Clean, readable, synthesizable Verilog HDL
- Cadence Encounter® RTL Compiler synthesis scripts
- Documentation – integration and user guide, release notes
- Sample verification testbench
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