The so_ip_srio_ctrl is a soft core implementation of Serial RapidIO controller as defined in the RapidIO specification 2.2.
So_ip_srio_ctrl soft core is fully compliant with the RapidIO 2.2 specification, and supports 1.25, 2.5, 3.125, and 5.0 Gbit/s data transfer rates.
So_ip_srio_ctrl core implements physical, transport and link layers, as defined in the RapidIO specification. It uses Xilinx's MGT transceivers to implement physical signaling required by the RapidIO specification. For the interface with the host processor IP core uses a highly configurable user interface.
So_ip_srio_ctrl core is delivered with fully automated testbench and a complete set of tests allowing easy package validation at each stage of SoC design flow.
The so_ip_srio_ctrl design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset. The so_ip_srio_ctrl core can be evaluated using Xilinx Evaluation Platforms before purchase. This is achieved by using a time-limited demonstration bit file for the selected Xilinx evaluation platform that allows the user to connect it’s Serial RapidIO enabled device to the So-Logic's so_ip_srio_ctrl core and evaluate system performance under different transfer scenarios.