Serial RapidIO IP Core
allows easy implementation of add-on third party bus interfaces and/or other standard bus interface. IP core also has internal multi-channel DMA desciprot based, controller that fully exploits AHB protocol features and thus supports highest available data throughput and back to back packet transmissions.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
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