PMCC_SER12G is a macro-block designed for robust 8.5-11.3Gb/s data 32:1 serialization independent on data coding. The serializer (except 32 bit inputs) is implemented based on differential CML logic for robust operation under strong noise coupling through power, ground and substrate. The 32 bit wide data stream (CMOS levels) coming from a FEC or another digital block is converted to differential CML levels, serialized and retimed to remove even/odd bit distortion, shape the eye and remove jitter. Serial data is shipped out through a differential 50Ω terminated (each output) data buffer. Multiple dividers (including fractional N) are implemented for support of different clocking modes: 79:85, 85:79 (FEC+G.709) 14:15, 15:14 (FEC only) 237:239, 239:237 (G.709 only) 255:239, 239:255 (add FEC to G709 frame) when macro is integrated with a complimentary deserializer. All biasing currents are programmable within +/-30% for operational margin estimation. DC test points permit to measure internal temperature, bias voltages and ground potential. Loop-back I/Os are integrated for link testing purposes. VCXO PLL is included for convenient reference clock generation by using an external high quality oscillator. Layout is designed using IBM CMOS10LPE 5_01_00_01_LD metal stack. Control functions and layout configuration can be customized upon special agreement.
- Data-rates from 8.5Gb/s to 11.3Gb/s.
- Digital 32-bit input
- Output CML 50Ω terminated
- Output swing 400mV or 250mV p-p SE
- Output data line rate retiming
- Low power consumption (110mW)
- 1.2V and 1.8V power supplies
- Clock synthesizer (including ∑Δ)
- LOL detection
- Adjustable (+/-30%) bias currents
- DC test points.
- Integrated temperature sensor
- Stand-by mode
- Loop back signal input/output.
- Clock monitor output
- VCXO control PLL
- GDS, netlist, documentation, schematics, testbench.