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Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC
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SHA-1 Secure Hash Function
The Alma Technologies SHA1 core is a high performance implementation of the SHA-1 (Secure Hash Algorithm 1) one-way cryptographic hash function, compliant with FIPS 180-1. The core is composed of two main units, the SHA1 Engine and the Padding Unit. The SHA1 Engine applies the SHA1 loops on a single 512-bit message block, while the Padding Unit splits the input message into 512-bit blocks and performs the message padding on the last block of the message.
The processing of one 512-bit block is performed in 82 clock cycles and the bit-rate achieved is 6.24Mbps / MHz on the input of the SHA1 core.
The SHA1 core is equipped with easy-to-use fully stallable interfaces both for input and output. These are designed to permit the user’s application to stop the data stream from the core when it is not able to receive data or to stop the input stream towards the core according to data arrival rate.
The processing of one 512-bit block is performed in 82 clock cycles and the bit-rate achieved is 6.24Mbps / MHz on the input of the SHA1 core.
The SHA1 core is equipped with easy-to-use fully stallable interfaces both for input and output. These are designed to permit the user’s application to stop the data stream from the core when it is not able to receive data or to stop the input stream towards the core according to data arrival rate.
Features
- Compliant to FIPS 180-1 specification of SHA-1.
- Bit padding internally implemented.
- Supports 2^64-1 bits maximum message length.
- Supports input message length multiple of 8-bit.
- Initial value of the chaining variables selected before synthesis.
- 82 processing cycles per 512-bit message block.
- Fully stallable input and output interfaces,
- ideal for streaming applications.
- Fully portable HDL source code
- Single clock domain and strictly positive edge triggered design using only D-type FFs
Deliverables
- Clear text VHDL or Verilog RTL source for ASIC designs, or pre-synthesized & verified Netlist for Altera, Lattice, Microsemi and Xilinx FPGA and SoC devices
- Release Notes, Design Specification and Integration Manual documents
- Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
- Self checking testbench environment, including sample BAM generated test cases
- Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts
Applications
- Data integrity
- Bulk Encryption
- High speed networking equipment
- Secure wireless applications
Block Diagram of the SHA-1 Secure Hash Function IP Core
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