SHA-1 Secure Hash Function
The processing of one 512-bit block is performed in 82 clock cycles and the bit-rate achieved is 6.24Mbps / MHz on the input of the SHA1 core.
The SHA1 core is equipped with easy-to-use fully stallable interfaces both for input and output. These are designed to permit the user’s application to stop the data stream from the core when it is not able to receive data or to stop the input stream towards the core according to data arrival rate.
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Block Diagram of the SHA-1 Secure Hash Function IP Core

SHA1 IP
- Tunable HMAC accelerator - compliant with all hash functions (SHA1, SHA2, SM3, SHA3) - optional SCA protection
- HASH Accelerator with SHA-3, SHA-2, SHA-1
- HMAC Accelerator with SHA-3, SHA-2, SHA-1
- HASH Core, providing MD5, SHA1 and SHA256. Includes DMA and AXI Interface
- Secure software implementation of SHA-1, SHA-2 and HMAC-SHA-256
- SHA-1 Processor