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PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
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SHA-256/224, balanced version
XIP3022B from Xiphera is a balanced Intellectual Property (IP) core implementing the secure hash algorithms SHA-224 and SHA-256 as specified in the Secure Hash Standard published by the National Institute of Standards and Technology (NIST). The message is parsed and padded into 512 bits long message blocks, and the resulting message digest (hash value) is either 256 or 224 bits long.
XIP3022B has been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of XIP3022B does not rely on any FPGA manufacturer-specific features.
XIP3022B has been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of XIP3022B does not rely on any FPGA manufacturer-specific features.
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Block Diagram of the SHA-256/224, balanced version IP Core
