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SHA-3 Secure Hash Function Core
The SHA-3 is a high-throughput, area-efficient hardware implementation of the SHA-3 cryptographic hashing functions, compliant to NISTS’s FIPS 180-4 and FIPS 202 standards.
Encryption IP Core from CAST, Inc.The core implements all the fixed-length and extendable hashing functions provisioned by these standards. The hashing function is synthesis-time configurable; a version supporting run-time hashing function selection can be made available upon request.
The SHA-3 core’s processing bitrate is impressively high even in its minimum throughput configuration, for which it processes 24 to 56 bits per cycle depending on the hashing function. This high throughput can scale to practically meet any processing rate. The number of hashing rounds per clock is configurable at synthesis time, allowing users to scale performance at the cost of silicon resources when desired.
The core is designed for ease of use and integration and adheres to industry best-standards coding and verification practices. It requires no assistance from a host pro-cessor, and uses standard AMBA® AXI4-Stream interfaces for input and output data. Technology mapping, timing closure, and scan insertion are trouble-free, as the core contains no multi-cycle or false paths, and uses only rising-edge-triggered D-type flip-flops, no tri-states, and a single-clock/reset domain. Its reliability and low risk have been proven through rigorous verification and FPGA validation.
Encryption IP Core from CAST, Inc.The core implements all the fixed-length and extendable hashing functions provisioned by these standards. The hashing function is synthesis-time configurable; a version supporting run-time hashing function selection can be made available upon request.
The SHA-3 core’s processing bitrate is impressively high even in its minimum throughput configuration, for which it processes 24 to 56 bits per cycle depending on the hashing function. This high throughput can scale to practically meet any processing rate. The number of hashing rounds per clock is configurable at synthesis time, allowing users to scale performance at the cost of silicon resources when desired.
The core is designed for ease of use and integration and adheres to industry best-standards coding and verification practices. It requires no assistance from a host pro-cessor, and uses standard AMBA® AXI4-Stream interfaces for input and output data. Technology mapping, timing closure, and scan insertion are trouble-free, as the core contains no multi-cycle or false paths, and uses only rising-edge-triggered D-type flip-flops, no tri-states, and a single-clock/reset domain. Its reliability and low risk have been proven through rigorous verification and FPGA validation.
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Block Diagram of the SHA-3 Secure Hash Function Core IP Core
