The SHA cores provide implementation of cryptographic hashes SHA-1 (core SHA1), SHA-2 (cores SHA2-256 and SHA2-512).
The cores utilize “flow-through” design that can be easily included into the data path of a communication system or connected to a microprocessor: the core reads the data via the D input and outputs the hash result via its Q output. Data bus widths for both D and Q are parameterized.
The design is fully synchronous and is available in both source and netlist form.
- Completely self-contained; does not require external memory
- SHA1 supports SHA-1 per FIPS 180-1, SHA2-256 and SHA2-512 support SHA-2 per FIPS 180-2.
- HMAC option is available with flow-through and microprocessor-friendly (-SK) interfaces for the key input.
- Flow-through design; flexible data bus width
- Test bench provided
- Message digest calculation
- Digital signature (DSA) algorithm of the Digital Signature Standard (DSS) per FIPS-186
- Security protocols, including
- TLS (RFC 2246, RFC 4346)
- SSL v3
- PGP (RFC 2440)
- SSH (RFC 4251)
- S/MIME (PKCS #7, RFC 3852)
- IPSec (RFC 2404, RFC 4301)
Block Diagram of the SHA1, SHA2 Cryptographic Hash Cores IP Core