The single 12-bit 2.5-GSPS ADC has build-in Track & Hold and an interleaved quantizer array for power-efficiency and low bit-error-rate. The ADC is self-calibrated for matching and linearity.
- Differential analog and clock inputs with on-chip termination.
- Built-in reference and bias circuitry.
- Built-in calibration reference.
- Built-in ESD protection.
- Ultra high sample rate
- Low bit-error-rate (1E-18)
- High input bandwidth (2 GHz)
- RTL for calibration
- Verilog-A model
- (US export restrictions apply)
- High-bandwidth communications
- Cable / Set top box
- Test & Measurement
- Radar / Lidar
Block Diagram of the Single 12-bit 2.5-GSPS ADC IP Core