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Single- and double-precision IEEE-754 floating-point unit
The GRFPU is an IEEE-754 compliant floating-point unit, supporting both single and double precision operands. The pipelined design combines high throughput with low latency, providing up to 200 MFLOPS on a 0.18 um ASIC process. The host interface is clean and versatile, simplifying the interfacing to processor pipelines and DSPs. The accuracy and convergence of the FPU algorithms have been proven mathematically, and the implementation has been validated with more than 20 million test vectors.
The GRFPU can be use stand-alone or attached to the LEON SPARC processor through the LEON FPU Control unit (GRFPC). The control unit receives SPARC FPU instructions (FPOP) from the LEON integer unit, and schedules them for execution by the FPU. The FPOPs are executed in parallel with other integer instructions, the LEON pipeline is only stalled in case of operand or resource conflicts. The GRFPC also includes the FPU register file, the processor floating-point status register (FSR) and a single-entry deferred trap queue. The GRFPC is available for LEON2, LEON2-FT and the upcoming LEON3 processor.
The GRFPU can be use stand-alone or attached to the LEON SPARC processor through the LEON FPU Control unit (GRFPC). The control unit receives SPARC FPU instructions (FPOP) from the LEON integer unit, and schedules them for execution by the FPU. The FPOPs are executed in parallel with other integer instructions, the LEON pipeline is only stalled in case of operand or resource conflicts. The GRFPC also includes the FPU register file, the processor floating-point status register (FSR) and a single-entry deferred trap queue. The GRFPC is available for LEON2, LEON2-FT and the upcoming LEON3 processor.
Features
- IEEE-754 compliant, supporting all rounding modes and exceptions
- Operations: add, subtract, multiply, divide, square-root, convert, compare, move, abs, negate
- Data formats: single and double precision (32- and 64-bit floats)
- Fully pipelined, 3 clock cycles latency for all operations except divide and square-root
- Non-blocking parallel execution of divide and square-root operations
- Clean and versatile interface
- LEON FP Control unit available
- Supports all SPARC V8 floating-point instructions
- 200 MHz (200 MFLOPS) on a typical 0.18um standard cell process using less than 100 kgates
- 65 MHz (65 MFLOPS) on a Virtex-II FPGA using approximately 8,500 LUTs
- SEU-hardened (fault-tolerant) version available
Deliverables
- VHDL Source Code
- EDIF netlist
- VHDL test bench
- Validation test software (C)
- ModelSim simulation model
- Technical documentation
- Synthesis scripts
- Technical support
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