Noesis Technologies ntHDLC single channel High-Level Data Link Controller (HDLC) is a full-duplex transceiver with independent transmit and receive units for synchronous framing bit-level HDLC protocol operations. The ntHDLC can handle interframe and delimiting flags, frame check sequence based on CCITT CRC16/CRC32 polynomial, normal or transparent transmission modes, abort generation and detection. The system interface is very flexible and can be adapted towards FIFO, uP, or DMA controllers. The transmit and receive units and their associated control and status logic are independent. This partitioning strategy enables the Tx and Rx units to be instantiated in different place and/or level of the design hierarchy. Each unit (Tx, Rx and back-end interface) has its own clock domain with synchronous clock enable. Communication between the various clock domains is achieved via synchronization logic blocks.
- Single port synchronous serial line interface.
- Flag/Abort Generation/Detection.
- Zero Insertion/Deletion.
- Non-octet alignment detection.
- CCITT CRC-16 Generation and Checking.
- NRZ/NRZI encoding/decoding.
- Transparent mode support.
- Receive FIFO overrun detection.
- Transmit FIFO underrun detection.
- Frame status and frame length indicators.
- Runt frame detection.
- Seperate clocks for Tx and RX interfaces.
- Supports fllag in interframe-time fill.
- 8-bit parallel back-end interface.
- Fully commented synthesizable VHDL or Verilog source code or FPGA netlist.
- VHDL or Verilog test benches and example configuration files.
- Comprehensive technical documentation.
- Technical support.
Block Diagram of the Single Channel HDLC Controller IP Core