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The 10/25/50Gbps Ethernet PCS Core is compliant with the IEEE802.3 10/25Gbps and the 25G Ethernet Consortium 25Gbps Ethernet specifications allowing systems to support link speeds above 10Gbps, with no increase of the Trace and/or Cable interconnect density.
The Core can also be used with an embedded 50Gbps Serdes to implement single lane 50Geth interfaces.
The Core implements the standard IEEE 802.3 Clause 49 scrambler / descrambler and the 64b/66b encoder / decoder
The RS-FEC for 25Gbps and 50Gbps Serdes with NZR modulation uses RS(528, 514) codewords allowing correction of up to seven 10-Bit symbols within 514 symbols and the RS-FEC for 50Gbps Serdes with PAM4 modulation uses RS(544, 514) codewords allowing correction of up to 15 10-Bit symbols within 514 symbols.
With RS-FEC a MLD module distributes data across 4 virtual lanes. The 4 virtual lanes are then transcoded into RS-FEC codewords and transferred on the 25 / 50Gbps serial lane.
On receive, the MLD re-aligns the serial data stream to the RS-FEC codeword boundaries for allowing error correction and decode.
The Core optionally supports the IEEE Clause 74 Firecode FEC (FC-FEC) in addition to the IEEE Clause 91 Reed Solomon FEC (RS-FEC).
The RS-FEC and FC-FEC error propagation to the PCS can be bypassed with software programming or can be removed with a synthesis option to reduce the Core latency.
On the application side, the Core implements a 64-Bit XGMII (10 Gigabit Media Independent Interface). On the line side, the Core implements a flexible 20, 40 or 64-bit parallel interface connectable to Industry standard embedded 10.3125Gbps, 25.78125Gbps and 51.5625Gbps Serdes macros.
The PCS Core can be used with MorethanIP Link Training and Autonegotiation Cores to design flexible backplane interconnection solutions.
The Core is optimized for latency and can be used to design Synchronous Ethernet applications
The MorethanIP Clause 73 Autonegotiation Core is fully generic and supports ‘Next Page’ negotiations to select the, non IEEE, 25Geth and 50Geth modes of operation.
The Core is delivered in generic synthesizable technology independent Verilog HDL code.
The Core is delivered with a comprehensive verification environment and expert MorethanIP technical and application support.
Single Lane 10/25/50 Gigabit Ethernet PCS Core
The 10/25/50Gbps Ethernet PCS Core is compliant with the IEEE802.3 10/25Gbps and the 25G Ethernet Consortium 25Gbps Ethernet specifications allowing systems to support link speeds above 10Gbps, with no increase of the Trace and/or Cable interconnect density.
The Core can also be used with an embedded 50Gbps Serdes to implement single lane 50Geth interfaces.
The Core implements the standard IEEE 802.3 Clause 49 scrambler / descrambler and the 64b/66b encoder / decoder
The RS-FEC for 25Gbps and 50Gbps Serdes with NZR modulation uses RS(528, 514) codewords allowing correction of up to seven 10-Bit symbols within 514 symbols and the RS-FEC for 50Gbps Serdes with PAM4 modulation uses RS(544, 514) codewords allowing correction of up to 15 10-Bit symbols within 514 symbols.
With RS-FEC a MLD module distributes data across 4 virtual lanes. The 4 virtual lanes are then transcoded into RS-FEC codewords and transferred on the 25 / 50Gbps serial lane.
On receive, the MLD re-aligns the serial data stream to the RS-FEC codeword boundaries for allowing error correction and decode.
The Core optionally supports the IEEE Clause 74 Firecode FEC (FC-FEC) in addition to the IEEE Clause 91 Reed Solomon FEC (RS-FEC).
The RS-FEC and FC-FEC error propagation to the PCS can be bypassed with software programming or can be removed with a synthesis option to reduce the Core latency.
On the application side, the Core implements a 64-Bit XGMII (10 Gigabit Media Independent Interface). On the line side, the Core implements a flexible 20, 40 or 64-bit parallel interface connectable to Industry standard embedded 10.3125Gbps, 25.78125Gbps and 51.5625Gbps Serdes macros.
The PCS Core can be used with MorethanIP Link Training and Autonegotiation Cores to design flexible backplane interconnection solutions.
The Core is optimized for latency and can be used to design Synchronous Ethernet applications
The MorethanIP Clause 73 Autonegotiation Core is fully generic and supports ‘Next Page’ negotiations to select the, non IEEE, 25Geth and 50Geth modes of operation.
The Core is delivered in generic synthesizable technology independent Verilog HDL code.
The Core is delivered with a comprehensive verification environment and expert MorethanIP technical and application support.
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Block Diagram of the Single Lane 10/25/50 Gigabit Ethernet PCS Core
Ethernet PCS IP
- 10-Gbps Ultra-Low Latency Ethernet MAC & PCS (10GBASE-R)
- 40-Gbps Ultra-Low Latency Ethernet MAC & PCS (40GBASE-R4)
- 100-Gbps Ultra-Low Latency Ethernet MAC & PCS (100GBASE-R4, 100GBASE-R10)
- 25-Gbps Ultra-Low Latency Ethernet MAC & PCS + RS-FEC
- 10 Gigabit Ethernet 10GBase-R PCS Core
- 25G LL MAC /PCS Ethernet IP for FPGA