TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling needs. It has features like clocking and clock & data recovery, Serialization and De-Serialization of Data, 128/132b data coding, Receiver detection.
TERMINUS CIRCUITS’s USB 3.1 PHY uses 32/16bit Data PIPE interface. It also supports lower power management’s states like P0s, P1, P1-sub-states and P2. USB 3.1 PHY IP is available in TSMC 55nm LP process.
* A limited number of Test Chips manufactured in TSMC 55LP (Single lane and Quad Lanes) are available for Early customers. Contact us for more details.
- - Parallel data widths of 8bits and 16bits
- - QUAD configuration (4TX and 4RX), Single lane configuration (1TX and 1RX)
- - Support signal loss and receiver detection using programmable multi-tap
- - Support 1m cable
- - High speed low Jitter (0.17UI) 10GHz PLL
- - Operation across a wide temperature range (-40 C to +125 C)
- - Higher Bandwidth in X4 mode.
- - Lowest power consumption per Gbps data rates
- - Supports higher loss channel
- - Documentation
- - Netlist
- - Timing library
- - Register map
- - Verilog
- - IBIS-AMI models
- - LEF views
- - LVS Schematic
- - DRC reports
- - Silicon
- Automotive – Infotainment
- Multi-Functional Printers
- LED TV
- Laptops / Desktop Computers
- Portable Medical Devices
- Smart Phones / Tablets