TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol and its signalling needs. It has features like clocking and clock & Data recovering, Serialization and De-Serialization of Data, 8/10b, data coding, Receiver detection.
TERMINUS CIRCUITS PCIe GEN 2.0 PHY uses 32/16bit Data PIPE interface. It also supports lower power management states like L0s, L1, L1-sub-states and L2. PCIe Gen 2.0 PHY IP is available in TSMC 65nm GP process.
* A limited number of Test Chips manufactured in TSMC 65GP (Single lane and Quad Lanes) are available for Early customers. Contact us for more details.
- - Quad PCIe 5/2.5 Gbps per lane
- - Tight skew control of less than 1UI between lanes of the PMA
- - Multi-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
- - Lowest latency
- - Continuous time linear equalizer (CTLE) with programmable settings
- - Programmable/automatic calibration of key circuits
- - Support for bifurcation and quadfurcation modes
- - Multi-tap Rx DFE (decision feedback equalizer)
- - Programmable int./ext. loopback modes between TX and RX
- -SRnS (Separate Reference no Spread) suppor
- - Includes ESD structures
- - Operation across a wide temperature range (-40 C to +125 C)
- - Higher Bandwidth in X4 mode.
- - Lowest power consumption per Gbps data rates
- - Supports higher loss channel
- - Documentation
- - Netlist
- - Timing library
- - Register map
- - Verilog
- - IBIS-AMI models
- - LEF views
- - LVS Schematic
- - DRC reports
- - Silicon
- Enterprise computing
- Storage networks
- GPU interfacing
- Server connectivity
- Network-on-Chip (NoC)