Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in GF 28SLP process
TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
You must be registered with the D&R website to view the full search results, including:
-
Complete datasheets for products
- Contact Suppliers for information
