400MHz, 12-bit High Speed Delta Sigma ADC for 5G, LiDAR and Imaging
Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS’s USB 3.1 PHY uses 32/16bit Data PIPE interface. It also supports lower power management’s states like P0s, P1, P1-sub-states and P2. USB 3.1 PHY IP is available in TSMC 28nm HPC process.
* A limited number of Test Chips manufactured in TSMC 28HPC (Single lane and Quad Lanes) are available for Early customers. Contact us for more details.
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USB GEN1 IP
- USB 3.2 Gen1 / Gen2 Device Controller IP
- USB 3.1 PHY IP ((10G/5G),Silicon proven in TSMC 28HPC+)
- USB 3.2 PHY IP ((20G/10G),Silicon proven in UMC 28HPC+)
- USB 3.1 Gen1 / Gen2 Device Controller IP
- 1.125G - 8G/10G SerDes IP, Supports (PCIe Gen1/2/3, USB 3.0 SuperSpeed, SATA Gen1/2/3, JESD204B and SGMII / QSGMII) standards (Silicon proven in ST 28 FDSOI)
- USB 3.1 PHY IP ((10G/5G),Silicon proven in UMC 28HPC+)