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250MHz Multi-channel High Speed Analog Front-End (AFE) for LiDAR, 5G and imaging
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Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling needs. It has features like clocking and clock & data recovery, Serialization and De-Serialization of Data, 8/10b data coding, Receiver detection.
TERMINUS CIRCUITS’s USB 3.1 PHY uses 32/16bit Data PIPE interface. It also supports lower power management’s states like P0s, P1, P1-sub-states and P2. USB 3.1 PHY IP is available in TSMC 28nm HPC process.
* A limited number of Test Chips manufactured in TSMC 28HPC (Single lane and Quad Lanes) are available for Early customers. Contact us for more details.
TERMINUS CIRCUITS’s USB 3.1 PHY uses 32/16bit Data PIPE interface. It also supports lower power management’s states like P0s, P1, P1-sub-states and P2. USB 3.1 PHY IP is available in TSMC 28nm HPC process.
* A limited number of Test Chips manufactured in TSMC 28HPC (Single lane and Quad Lanes) are available for Early customers. Contact us for more details.
Features
- - Parallel data widths of 8bits and 16bits
- - QUAD configuration (4TX and 4RX), Single lane configuration (1TX and 1RX)
- - Support signal loss and receiver detection using programmable multi-tap
- & de-emphasis
- - Support 1m cable
- - High speed low Jitter (0.17UI) 10GHz PLL
- - Operation across a wide temperature range (-40 C to +125 C)
Benefits
- - Higher Bandwidth in X4 mode.
- - Lowest power consumption per Gbps data rates
- - Supports higher loss channel
Deliverables
- - Documentation
- - Netlist
- - Timing library
- - Register map
- - Verilog
- - IBIS-AMI models
- - LEF views
- - LVS Schematic
- - DRC reports
- - Silicon
Applications
- Automotive – Infotainment
- Multi-Functional Printers
- LED TV
- Laptops / Desktop Computers
- Portable Medical Devices
- Smart Phones / Tablets
View Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 28HPC process full description to...
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USB GEN1 IP
- USB 3.1 Gen.1 TYPE-C PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process
- Multi-Link Multi-Protocol SerDes - USB 3.1 PHY IP Gen1 TSMC 16FF+LL
- Multi-Link Multi-Protocol SerDes - USB 3.1 PHY IP Gen1 TSMC 16FF+GL
- SiFive USB3.2 Gen2 Device Controller IP Core
- SiFive: USB3.0 DR-OTG Controller IP Core
- Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 55LP process