Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 55LP process
TERMINUS CIRCUITS’s USB 3.1 PHY uses 32/16bit Data PIPE interface. It also supports lower power management’s states like P0s, P1, P1-sub-states and P2. USB 3.1 PHY IP is available in TSMC 55nm LP process.
* A limited number of Test Chips manufactured in TSMC 55LP (Single lane and Quad Lanes) are available for Early customers. Contact us for more details.
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USB GEN1 IP
- USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm,6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
- USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core
- USB 3.0 Gen1 / Gen2 Device Controller IP
- USB 3.1 Gen1 / Gen2 Device Controller IP
- USB 3.0 Gen1 / Gen2 Host Controller IP
- USB 3.1 Gen.1 TYPE-C PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process