Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 65GP process
TERMINUS CIRCUITS’s USB 3.1 PHY uses 32/16bit Data PIPE interface. It also supports lower power management’s states like P0s, P1, P1-sub-states and P2. USB 3.1 PHY IP is available in TSMC 65nm GP process.
* A limited number of Test Chips manufactured in TSMC 65GP (Single lane and Quad Lanes) are available for Early customers. Contact us for more details.
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USB GEN1 IP
- USB 3.2 Gen1 / Gen2 Device Controller IP
- USB 3.1 PHY IP ((10G/5G),Silicon proven in TSMC 28HPC+)
- USB 3.2 PHY IP ((20G/10G),Silicon proven in UMC 28HPC+)
- USB 3.0 Gen1 / Gen2 Device Controller IP
- 1.25G-12.5G SerDes IP, Supports (PCIe Gen1/2, USB 3.0, SATA Gen 1/2/3) (Silicon Proven in SMIC 40LL)
- USB 3.1 Gen.1 TYPE-C PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process