English
You are here:
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY in Samsung 28LPP process
TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol and its signalling needs. It has features like clocking and clock & Data recovering, Serialization and De-Serialization of Data, 128/130b, data coding, Receiver detection.
TERMINUS CIRCUITS’s PCIe GEN 3.0 PHY uses 32/16bit Data PIPE interface. It also supports lower power management states like L0s, L1, L1-sub-states and L2. PCIe Gen 3.0 PHY IP is available in Samsung 28nm LPP process.
* A limited number of Test Chips manufactured in Samsumg 28LPP (Single lane and Quad Lanes) are available for Early customers. Contact us for more details.
TERMINUS CIRCUITS’s PCIe GEN 3.0 PHY uses 32/16bit Data PIPE interface. It also supports lower power management states like L0s, L1, L1-sub-states and L2. PCIe Gen 3.0 PHY IP is available in Samsung 28nm LPP process.
* A limited number of Test Chips manufactured in Samsumg 28LPP (Single lane and Quad Lanes) are available for Early customers. Contact us for more details.
View Single Lane and Quad Lane 8Gbps PCIe3.0 PHY in Samsung 28LPP process full description to...
- see the entire Single Lane and Quad Lane 8Gbps PCIe3.0 PHY in Samsung 28LPP process datasheet
- get in contact with Single Lane and Quad Lane 8Gbps PCIe3.0 PHY in Samsung 28LPP process Supplier
PCIe 3.0 PHY IP
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- PCIe 5.0 SerDes PHY
- Complete PCIe 4.0 Soft IP supporting endpoint, root port, switch, bridge and advanced features such as SR-IOV, multi-function, data protection (ECC, ECRC), ATS, TPH, AER and more
- Customizable Embedded Multi-port PCIe Switch
- PCIe 5.0 Controller
- PCIe 5.0, 4.0, 3.1/3.0 Root Port, Endpoint, Dual-mode, Controller IP Core with Built-in Many-Channel DMA (vDMA), Legacy DMA, and Configurable AMBA AXI Interconnect