Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 32 k

Features

• Smart periphery design to reach the highest density
• Memory designed with SVT MOS for periphery and SVT
• HD PRBC from TSMC for memory core
• Flexible architecture
• To offer several performance trade-offs for any memory
• size
• Multiple form factors proposed by the generator for a
• given capacity
• Variable write mask capability
• Easy integration
• Data range flexibility allows easy addition of bits for
• redundancy or ECC purposes
• Address range flexibility allows easy addition of single
• rows for redundancy purposes
• The Dolphin Integration quality
• Complete mismatch validation of the memory architecture
• taking into account local and global dispersion
• Optional BIST for industrial fabrication test of instances
• Compliance with TSMC IP 9000 qualification process

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