Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k

Features

• Configuration
• SVT transistors for memory periphery
• uHD HVT pushed rule bit-cell from foundry
• High speed
• More than 295 MHz in worst case
• Architecture specifically suited for MCU
• Smart periphery design for significant gain in density
• Power reduction features
• Data retention mode at 1.2 V to divide leakage by a factor of 7 compared to simple stand by mode
• Byte write capability
• Easy integration
• MUX options
• Data range flexibility allows easy addition of bits for redundancy or ECC purposes
• Address range flexibility allows easy addition of single rows for redundancy purposes
• The Dolphin quality
• Complete mismatch validation of the memory architecture taking into account local and global dispersion
• Optional BIST for industrial fabrication test of instances

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