400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
Single Port Register File compiler - Memory optimized for high density and high speed - Dual voltage - compiler range up to 40 k
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- Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k
- Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k