Single Port Register File compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 40 k

Features

• REACH HIGHEST DENSITY
• Smart periphery design for significant gain in density
• EXTEND BATTERY LIFE
• Data retention mode at 1.2 V and 0.9 V to divide drastically the leakage compared to simple stand by mode
• Byte write capability
• MAKE INTEGRATION EASIER
• Data range flexibility allows easy addition of bits for redundancy or ECC purposes
• Address range flexibility allows easy addition of single rows for redundancy purposes
• ENABLE RIGHT ON FIRST PASS DESIGN
• Complete mismatch validation of the memory architecture taking in account local and global dispersion
• Extended validation for high coverage rate of the compiler

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