Single Port Register File compiler - Memory optimized for ultra high density and high speed - compiler range up to 20 k

Features

• Migration of an existing architecture already available for other processes (130, 90, 55 nm)
• High speed
• More than 230 MHz in worst case
• SVT MOS for periphery
• Architecture specifically suited for display driver
• Smart periphery design for significant gain in density
• Designed with Pushed rule bit cell from foundry
• 100 um maximum cell height
• Designed with 3 metal layers only
• Power reduction features
• Data retention mode at 1.5 V to divide leakage by a 40% compared to simple stand by mode
• Optional Byte write (MUX 4) and bit-wise write capability (MUX 8)
• Easy integration
• MUX options
• Data range flexibility allows easy addition of bits for redundancy or ECC purposes
• Address range flexibility allows easy addition of single rows for redundancy purposes
• The Dolphin quality
• Complete mismatch validation of the memory architecture taking into account local and global dispersion
• Optional BIST for industrial fabrication test of instances

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