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Single Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process
UMC 55nm SP Low_K Logic process synchronous high density Single Port SRAM memory compiler with row-pair redundancy.
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Memory IP
- The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
- HBM Subsystem IP Gen2
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