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Single Port SRAM Compiler IP, UMC 40nm LP process
ULL Single Port SRAM with row redundancy, UMC 40nm LP process.
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Memory IP
- The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
- SiFive: HBM Subsystem IP Gen2
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm)
- Multi Rate SerDes PHY - TSMC 28nm HPC+
- sROMet compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 1M
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k