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MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes in TSMC (12nm, N5)
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Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 640 k
Foundry sponsored - Single Port SRAM compiler - TSMC 55 nm HV - Memory optimized for high density and Low power - compiler range up to 640 k
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