Camera SLVS-EC v.2.0 5.0Gbps / MIPI D-PHY v2-1 4.5Gbps combo Receiver 4-Lane
Single Port SRAM compiler - Memory optimized for high density and low power - Deep N Well supported - compiler range up to 320 k
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SRAM IP
- Memory (SRAM, DDR, NVM) encryption solution
- Complete Neural Processor for Edge AI
- Intrinsic ID Zign® 100 - Software implementation of SRAM PUF
- Intrinsic ID Zign® 200 - Software implementation of SRAM PUF with symmetric cryptography
- Intrinsic ID Zign® 300 - Software implementation of SRAM PUF with symmetric & asymmetric cryptography + PKI
- 32-bit SRAM/PROM Controller