Fastest multiplier only two cycles .
less resources occupied.
- Synthesizable, technology independent Verilog HDL Core.
- 32 bits floating-point arithmetic.
- IEEE 754 compliant
- High-speed fully pipelined architecture.
- Only 2 clock-cycles of latency.
- fastest Multiplier in the world.
- occupies less resources .
- Floating-point pipelines and arithmetic units.
- Floating-point processors.
Block Diagram of the Single precision floating-point 2 cycle's multiplier IP Core