Single precision (32bits) IEEE 754- 2008 standard Floating Point Generic Complex Matrix Multiplier IP core achieve the low latency high throughput in the FPGA/ASIC platforms. In StratixIII FPGA Device, Complex Matrix Multiplier [8x8] can achieve maximum operating clock frequency of 140MHz and throughput of 2MSPS with 153 clock cycle initial latency.
- 32-bit floating-point Complex Matrix Multiplier operation with supported dimensions of [NxN] where N=2, 4, 8, 16, 32 and so on.
- IEEE 754 compliant
- IP Core does not have fixed Output Latency .Instead, it uses Handshaking signals to interface with external circuitry
- Rounding is to the nearest even number
- Separate Status flags indicating overflow, underflow, divide by zero, infinity, not a number, denormalization and zero values for Real and Imaginary.
- Built in Debug Logic feature to simplify the debugging process
- Specifically designed for high-speed and high-performance floating point applications
- Fully synthesizable synchronous design with positive edge clocking
- Floating point Complex Matrix Multiplier IP Core Interface is available in Verilog - HDL source code and Netlist on target device/technology
- User Manual for Floating point Complex Matrix Multiplier IP Core Interface and Floating point Complex Matrix Multiplier IP Core Verification user manual
- Tools specific scripts for simulation and Synthesis