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Single Precision Floating Point Complex Multiplier
Single precision(32bits) IEEE 754- 2008 standard Floating Point pipeline complex multiplier IP core achieve the high throughput in the FPGA/ASIC platforms. In Stratix-III FPGA Device it can achieve maximum operating clock frequency of 160MHz and throughput of 160MSPS with 8 clock cycle initial latency.
Features
- 32-bit floating-point complex multiplier operation
- IEEE 754 compliant
- 8 stage pipelined architecture
- First in First out latency of 8 clock cycle
- IP core supports streaming inputs/outputs
- Rounding is to the nearest even number
- Built in Debug Logic feature to simplify the debugging process
- Status flags indicating overflow, underflow, denormalization, infinity , not a number and zero values
- Specifically designed for high-speed and high-performance floating point applications
- Fully synthesizable synchronous design with positive edge clocking
Deliverables
- Floating point complex multiplier IP Core Interface is available in Verilog - HDL source code and Netlist on target device/technology
- User Manual for Floating point complex multiplier IP Core Interface and Floating point complex multiplier IP Core Verification user manual
- Tools specific scripts for simulation and Synthesis
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