Single precision (32bits) IEEE 754- 2008 standard Floating Point sequential divider IP core achieve the low area high throughput in the FPGA/ASIC platforms. In Arria10 FPGA Device it can achieve maximum operating clock frequency of 400MHz and throughput of 400MSPS with 34 clock cycle initial latency. In ASIC 28nm TSMC technology it can achieve 600MHz clock frequency and corresponding throughput of 600MSPS with 34 clock cycle latency.
- 32-bit floating-point divider operation
- IEEE 754 compliant
- First in First out latency of 34 clock cycle
- Rounding is to the nearest even number
- Status flags indicating overflow, underflow, divide by zero, infinity, not a number, denormalization and zero values.
- Built in Debug Logic feature to simplify the debugging process
- Specifically designed for low area and high-performance floating point applications
- Fully synthesizable synchronous design with positive edge clocking
- Floating point Divider IP Core Interface is available in Verilog - HDL source code and Netlist on target device/technology
- User Manual for Floating point Divider IP Core Interface and Floating point Divider IP Core Verification user manual
- Tools specific scripts for simulation and Synthesis