Single Precision Floating Point Divider

Single precision (32bits) IEEE 754- 2008 standard Floating Point sequential divider IP core achieve the low area high throughput in the FPGA/ASIC platforms. In Arria10 FPGA Device it can achieve maximum operating clock frequency of 400MHz and throughput of 400MSPS with 34 clock cycle initial latency. In ASIC 28nm TSMC technology it can achieve 600MHz clock frequency and corresponding throughput of 600MSPS with 34 clock cycle latency.

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