Single precision (32bits) IEEE 754- 2008 standard Floating Point pipeline Inverse Square Root IP core achieve the high throughput in the FPGA/ASIC platforms. In Stratix III FPGA Device it can achieve maximum operating clock frequency of 220MHz and throughput of 220MSPS with 13 clock cycle initial latency.
- 32-bit floating-point Inverse Square Root operation
- IEEE 754 compliant
- 13 stage pipelined architecture
- First in First out latency of 13 clock cycle
- IP core supports streaming inputs/outputs
- Rounding is to the nearest even number
- Status flags indicating divide by zero, infinity, not a number and zero values.
- Built in Debug Logic feature to simplify the debugging process
- Specifically designed for high-speed and high-performance floating point applications
- Fully synthesizable synchronous design with positive edge clocking
- Floating point Inverse Square Root IP Core Interface is available in Verilog - HDL source code and Netlist on target device/technology
- User Manual for Floating point Inverse Square Root IP Core Interface and Floating point Inverse Square Root IP Core Verification user manual
- Tools specific scripts for simulation and Synthesis