Scalable, On-Die Voltage Regulation for High Current Applications
Slave HSSL Controller
The new IP core allows system designers to combine functional safety and security provided by AURIX™ with the wide range of functional possibilities brought to the table by the Xilinx devices. Linked devices can access and control each other’s internal and connected resources through the HSSL. The logiHSSL IP is prepared for the Xilinx Vivado Design Suite to enable quick and efficient resource implementations in the latest Xilinx All Programmable devices for use in the embedded systems that meet the highest safety standards.
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