The DPSMBUS is a fully-featured module based on the I2C protocol, which supports SMBus and PMBus functionalities.
It can operate as a DPSMBUSM – Master and DPSMBUSS – Slave. Due to SMBus and PMBus documentation, the module meets the requirements, both for SMBSDA and SMBSCK acceptable timing intervals.
The DSPMBUS module supports arbitration and clock synchronization, which is necessary for multi-master systems. The IP Core, as it’s been suggested in the SMBus documentation, has implemented a reaction on a stuck SMBSCK signal in a low state Ttimeoutmin.
DPSMBUS supports transmission speeds up to 3.4 Mb/s, which cover all three acceptable speeds for SMBus and PMBus:
The DPSMBUS in the slave mode has attached internal FIFO, which can store even up to 256 bytes. It is also possible to read the status of the transmission including a step where communication failed. Except for SMBSDA and SMBSCK, there is also SMBAlert, which is defined as an interrupt signal between master and slave devices. Due to the SMBAlert handler, DPSMBUS supports arbitration of slave devices.
The DPSMBUS in PMBus version accepts ALERT RESPONSE ADDRESS, GENERAL CALL, DEVICE DEFAULT ADDRESS, ZONE WRITE, and ZONE READ predefined addresses. Also, it is possible to perform group command protocol and even extended command functionality. There are included CONTROL and WRITE PROTECT signals along with their functionality for device supervision.