This PLL is designed for audio clock generation. The reference clock is 13.5MHz crystal or the input clock. It supports both 256X and 384X oversampling rates. For 256X, it can generate 13 sample rates and for 384X, it can generate 11 sample rates. In overall, it integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control oscillator (VCO), a current reference, two programmable dividers and other supportive circuits.
- Process: SMIC 0.13um 1P8M 1.2v/3.3v Logic Process
- Supply voltage: 3.3v +/-10%; 1.2v+/-10%
- Reference input: 13.5MHz crystal or external clock
- Clock output: 256*F0/384*F1 Where F0 can be: 192KHz/176.4KHz/96KHz/88.2KHz/48KHz/44.1KHz/32KHz/24KHz/22.05KHz/16KHz/12KHz/11.025KHz/8KHz Where F1can be: 96KHz/88.2KHz/48KHz/44.1KHz/32KHz/24KHz/22.05KHz/16KHz/12KHz/11.025KHz/8KHz
- Current: <2mA
- Operating temperature: 0~85°C