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Low Latency & size Interlaken core for ASIC or FPGA, up to 1,000Gbps, 32 lanes, 112G/lane
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SMIC 0.13um 1.2v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 50MHz to 500MHz. By setting DM(5:0) and DN(6:0) to different values according to different REFIN, CLK will be locked at the multiples of input frequency.
Features
- Process: SMIC 0.13um 1.2v/2.5v 1P6M/7M/8M CMOS logic process
- Supply voltage: 1.0v~1.2v~1.32v
- Current: <2.5mA
- Operating temperature: - 40°C ~ +25°C ~ +125°C
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