VeriSilicon SMIC 0.13um High-Density Standard Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13um Logic 1P8M Salicide 1.2/2.5V process, based on a nine track layout architecture.
The library supports most commonly used basic Boolean functions with multiple drive strengths. While satisfying the performance and power requirements, it was optimized for area efficiency.
- VeriSilicon SMIC 0.13um High-Density Standard Cell Library uses metal 1 only within the cells and supports design with four, five, six, seven or eight layers of metal.
- Databook in electronic format
- Verilog models and Synopsys synthesis models
- Candence Silicon Ensenble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist