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SMIC 0.13um General Process, 1.2V/2.5V Standard Cell Library
VeriSilicon SMIC 0.13um High-Density Standard Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13um Logic 1P8M Salicide 1.2/2.5V process, based on a nine track layout architecture.
The library supports most commonly used basic Boolean functions with multiple drive strengths. While satisfying the performance and power requirements, it was optimized for area efficiency.
The library supports most commonly used basic Boolean functions with multiple drive strengths. While satisfying the performance and power requirements, it was optimized for area efficiency.
Features
- VeriSilicon SMIC 0.13um High-Density Standard Cell Library uses metal 1 only within the cells and supports design with four, five, six, seven or eight layers of metal.
Deliverables
- Databook in electronic format
- Verilog models and Synopsys synthesis models
- Candence Silicon Ensenble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist
View SMIC 0.13um General Process, 1.2V/2.5V Standard Cell Library full description to...
- see the entire SMIC 0.13um General Process, 1.2V/2.5V Standard Cell Library datasheet
- get in contact with SMIC 0.13um General Process, 1.2V/2.5V Standard Cell Library Supplier
Standard Cell
- DesignWare HPC Design Kit contains high-speed and high-density memory instances and standard cell libraries
- 9 track Near Threshold Voltage standard cell library at TSMC 55 nm
- 40nm Low Leakage HD, Channel Length 40nm, ECO,HVT Logic Process Standard cell Library
- 40nm Low Leakage HD, Channel Length 40nm, ECO,LVT Logic Process Standard cell Library
- 40nm Low Leakage HD, Channel Length 40nm, ECO,RVT Logic Process Standard cell Library
- 40nm Low Leakage HD, Channel Length 40nm, LVT Logic Process Standard cell Library
