VeriSilicon SMIC 0.13um 1.2V/3.3V I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13um 1.2V/3.3V process. This library can take 5V tolerance. This library supports both Stagger I/O pads and Inline I/O pads. They are configurable and variable driving strength between 2mA - 24mA.
- VeriSilicon SMIC 0.13um 1.2V/3.3V I/O Cell Library supports design with six, seven or eight layers of metal.
- Databook in electronic format
- Verilog models and Synopsys synthesis models
- Candence Silicon Ensenble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist