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SMIC 0.13um High-Speed Synchronous Two-Port Register File
VeriSilicon SMIC 0.13um Synchronous Two-Port Register File optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13um Logic 1P8M Salicide 1.2/2.5(3.3)V process.
While satisfying speed and power requirements, it was optimized for area efficiency.
VeriSilicon SMIC 0.13um Synchronous Two-Port Register File uses four metal layers within the blocks and supports metal 6,7,8 as the top metal. Dummy bit cells are designed in with the intention to enhance reliability.
While satisfying speed and power requirements, it was optimized for area efficiency.
VeriSilicon SMIC 0.13um Synchronous Two-Port Register File uses four metal layers within the blocks and supports metal 6,7,8 as the top metal. Dummy bit cells are designed in with the intention to enhance reliability.
Features
- Two Ports (one read and one write)
- High Density
- High Speed
- Size Sensitive Self-time Delay for Fast Access Time
- Automatic Power Down
Deliverables
- Databook in electronic format
- Verilog models and Synopsys synthesis models
- Candence Silicon Ensenble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist
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High Speed
- Interlaken Protocol IP (High Speed Chip-To-Chip Interface)
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm)
- 10-bit, 12-bit, 14-bit, Low Speed SAR ADC in TSMC (180nm, 90nm, 65nm, 55nm, 40nm, 28nm, 16nm, 12nm)
- 12-bit, High Speed Current Steering DAC in TSMC (65nm, 40nm, 28nm, 16nm, 12nm)
- High speed NoC (Network On-Chip) Interconnect IP
- sROMet compiler - Memory optimized for high density and high speed - compiler range up to 2M