VeriSilicon SMIC 0.13um Synchronous Two-Port Register File optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13um Logic 1P8M Salicide 1.2/2.5(3.3)V process.
While satisfying speed and power requirements, it was optimized for area efficiency.
VeriSilicon SMIC 0.13um Synchronous Two-Port Register File uses four metal layers within the blocks and supports metal 6,7,8 as the top metal. Dummy bit cells are designed in with the intention to enhance reliability.
- Two Ports (one read and one write)
- High Density
- High Speed
- Size Sensitive Self-time Delay for Fast Access Time
- Automatic Power Down
- Databook in electronic format
- Verilog models and Synopsys synthesis models
- Candence Silicon Ensenble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist