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SMIC 0.13um High Vt Process, 1.2V/2.5V standard cell Library
VeriSilicon SMIC 0.13um High-Vt High-Density Standard Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13um Logic 1P8M Salicide 1.2/2.5V process, based on a nine track layout architecture.
The library supports most commonly used basic Boolean functions with multiple drive strengths. While satisfying the performance and power requirements, it was optimized for area efficiency.
The library supports most commonly used basic Boolean functions with multiple drive strengths. While satisfying the performance and power requirements, it was optimized for area efficiency.
Features
- VeriSilicon SMIC 0.13um High-Vt High-Density Standard Cell Library uses metal 1 only within the cells and supports design with four, five, six, seven or eight layers of metal.
Deliverables
- Databook in electronic format
- Verilog models and Synopsys synthesis models
- Candence Silicon Ensenble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist
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High Vt IP
- UMC 55nm LP LowK Logic Process standard synchronous high density single port SRAM memory compiler with high-Vt peripheral, but without write through.
- UMC 55nm LP LowK Logic Process standard synchronous high density single port SRAM memory compiler with row redundancy and high-Vt peripheral, but without write through.
- SMIC 65nm high speed standard cell library for Low-Vt LL logic process.
- 6.5 Track High Density and Low Power Standard Cell Library (HDSC) in TSMC (22ULL/22ULP, 28HPC+)
- 12 Track Ultra-High Speed Standard Cell Library (HSSC) in TSMC (16nm/12nm, 16FFC, 12FFC, 28HPC+, 40LP)
- SRAM on EF 28 Embedded Flash Platform in TSMC 28nm ESF3