This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 50MHz to 400MHz. By setting DM [5:0] and DN [7:0] to different values according to different REFIN, CLK will be locked at the multiples of input frequency. Moreover, by adjusting the value of DP [2:0] users can get a lower frequency clock output, CLKO, after CLK is divided by DP [2:0].
- Process: SMIC 0.18um 1.8v 1P6M CMOS logic process
- Supply voltage: 1.62v~1.8v~1.98v
- Current: <3mA
- Operating temperature: - 40C ~ +25C ~ +125C
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