This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution. The ADC includes internal sample/hold circuits, a capacitive DAC, a comparator, and logic control circuits. External reference voltage is needed. The voltage reference input can be adjusted to allow encoding from smaller analog voltage span to the full 12 bits of resolution. This ADC has dual speed modes, i.e., high speed and low speed, working in low speed mode could save some power. Moreover, it supports two running modes: free running and single running. In single running mode, SAR will switch to power down mode automatically so as to save power. The converter is designed to allow operating with the NSC800 and INS8080A derivative control bus which are driven directly by TRI-STATE output latches. The A/D mocks memory locations or I/O ports to the microprocessor and no interfacing logic is needed. The IP suits integrated auxiliary codec applications and multi-converter architectures in wireless or battery-operated products.