The analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution. The ADC includes a core internal SAR ADC and a 8-1 MUX. The internal SAR ADC includes sample/hold circuits, a capacitive DAC, a comparator and logic control circuits. This IP is typically used in touch screen application. Some types of input may need the reference voltage whereas the others may not, for example, when this IP acts as battery detector, external reference must be stable. In addition, the reference voltage input will be adjusted to allow encoding smaller analog voltage spanning to the full 12 bit resolution. The ADC has dual speed modes ¨C 1M/200K - working in 200K mode could save some power. Moreover, it supports two running modes: free running and single running. In single running mode, SAR will switch to power down mode automatically so as to save power. The converter is designed to allow operation with the NSC800 and INS8080A derivative control bus, with TRI-STATE output latches directly driving the data bus. The A/D appears like memory addresses or I/O ports to the microprocessor and no interfacing logic is needed. It is also suitable for integrated auxiliary codec applications and multi-converter architectures in wireless or battery-operated products.