32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
SMIC 0.18um 90% shrunk Single-Port/Dual-Port SRAM, Two-Port Register File and Diffusion ROM Compiler
The compiler supports a comprehensive range of word and bit lengths. While satisfying speed and power requirements, it is optimized for area efficiency.
VeriSilicon SMIC 0.16um Memory Compiler uses four layers within the blocks and supports metal 4, 5, or 6 as the top metal. Dummy bit cells are synthesized with the intention to enhance reliability.
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SMIC IP
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- USB 2.0 nanoPHY in SMIC (65nm)
- Duet Package of Embedded Memories and Logic Libraries for SMIC (65nm, 40nm)