The present IP is a VCC Detector (VDT) circuit. It detects the voltage level of its power supplies, AV18 and AV33. The normal operation voltage levels of AV18 and AV33 are 1.62v~1.98v and 3.0v~3.6v respectively. When the detected voltage AV18/AV33 increases across the detection level VR18/VR33, the corresponding output OUTP15/OUTP23 is generated as a high level logic. When the detected voltage AV18/AV33 decreases below the detection level VF18/VF33, the corresponding output OUTP15/OUTP23 is generated as a low level logic. This system consists of two comparator sub-circuits and needs an external bandgap. 1.8V power must be ready when 3.3V power is detected, otherwise no correct output appears. The output may be in the wrong voltage level during the power-up phase before the bandgap becomes stable, however, if the power supply’s rise time is longer than 5ms, this erroneous output will not occur.