The LVDS transceiver IP is a Serializer/Deserializer (SERDES) pair that transparently translates 12–bit parallel bus into serial stream. This single serial stream simplifies the transfer of 12-bit or less bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. In addition, this SERDES pair has built-in system and device test capability. The line loop back feature enables a user to check the integrity of the serial data transmission path of the transmitter and receiver while deserializing the serial data to parallel data at the receiver output. The local loop-back feature enables a user to check the integrity of the transceiver from the local parallel-bus side.