VeriSilicon SMIC 0.18um 1.8V/3.3V SSTL2 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.18um Logic 1P6M Salicide 1.8/3.3V process. This library is fully compliant with the EIA/JEDEC standard, JESD8-9B Stub Series Terminated Logic for 2.5V (SSTL2) updated in Oct 2002.
The SSTL2 provides MOS push-pull interface designs and is especially optimized for major memory applications. It is intended to improve operation in situations where busses must be isolated from relatively large stubs. Comparing to the LVTTL solution, SSTL2 has the advantages of lower voltage swing, lower power dissipation and higher immunity to generated noise because of the differential receiver.
There are two classes of output specifications for SSTL2, class I and class II, which are distinguished by drive requirements and application. Class I is basically applied for point-to-point configuration, such as network applications, and Class II is mostly applied for 266MHz DDR SDRAM signaling.
- SMIC 0.18um Logic 1P6M Salicide 1.8V/3.3V process
- 1.8V core and 2.5V External interface
- Meet SSTL2 DC input levels and SSTL2 AC output levels
- Cell count: 21 cells, which are 8 pad body, 2 power cut cell, 1 corner cell, 8 filler, 2 pad head
- Pad pitch: 40um
- Cell height: 234um
- Suitable for four, five, six metal layers physical design
- Easy interface with VeriSilicon SMIC 0.18um process standard I/O libraries
- Databook in electronic format
- Verilog models and Synopsys synthesis models
- Candence Silicon Ensenble Abstracts (LEF), Avanti! Apollo data, GDS II,
- LVS netlist