SMIC 0.25um 2.5V APLL

The present IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run up to 280MHz. By setting different values of DM[4:0] and DN[6:0] according to the different REFIN frequency, BAKO will be locked at the rising edge of REFIN and the output frequency (CKO) will be locked at the multiples of the input frequency.

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PLL phase locked loop IP

Phase Locked Loop (PLL) Frequency Synthesizer Core
Phase Locked Loop (PLL) Module
Phase Locked Loop (PLL) Macro
TSMC 12 FFC PLL_Clock Generator / Clock Synthesizer, (Fractional / Integer, 4GHz / 8GHz)
200 MHz—800 Mhz Phase Locked Loop IP Block
5GHz to 13.5GHz Phase Locked Loop IP Block

See more PLL phase locked loop IP >>

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